Processor, a circuit and a method for processing images in a parallel processor network

ABSTRACT

A processor, a circuit and a method for processing images in an analog parallel processor network. A processor comprises a plurality of circuits, a bias transistor and an output transistor. A circuit comprises a first transistor and a second transistor, which receive respective supply voltages and operate as current sources, providing an output voltage. A circuit further comprises a coefficient coupling, which receives the output voltage provided by the first transistor and the second transistor, providing a switching function for a circuit output current. A transistor in a coefficient coupling determines a mode of operation based on the output voltage, provided by the first transistor and the second transistor, and an input current. The circuit provides an output current of the circuit for further processing.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a processor, a circuit and amethod for processing images in a parallel processor network, and moreparticularly for processing images in an analog parallel processornetwork.

BACKGROUND OF THE INVENTION

[0002] A parallel processor network includes several identicalprocessors (cells) that are arranged in a regular form. Each cell has anincome signal, a dynamic state and an outcome signal.

[0003] The idea in a parallel processor network for processing images isthat one processor (cell) corresponds to one pixel, and therefore, it ispossible to provide a parallel processor network that is able for veryfast processing (in theory). A problem for integrating this kind of aparallel processor network into a chip is that the size of processorshave not been minimized to enable implementing integration of tens orhundreds of thousands of processors into a chip without lowering theliability.

[0004] In a parallel processor network, the cells are connected to theirneighboring cells (they can also be connected for example to all othercells in a parallel processor network), i.e., they affect to a dynamicstate of their neighboring cells. This affect correlatesstraightforwardly to the income of the cell and its own dynamic outcome.These features enable a real-time signal processing, because the dataprocessing occurs in all cells at the same time.

[0005] A parallel processor network can be implemented for processingimages, e.g. for filtering salt & pepper noise from an image. There hasbeen presented several methods for filtering noise from image, wherefromone of the generally used methods is median filters. A median filter isa special case of a ranked-order filter in which a median of the numberscan be chosen, but also any other ranked-order number unit can bechosen. These cases include for example finding a maximum or a minimumfrom a specified array of numbers. The operations, which use a methodbased on finding a maximum or a minimum from the specified array ofnumbers, are widely used in image processing, e.g., when mathematicalmorphology operations are implemented.

[0006] One special case of ranked order filtering is median filteringe.g., the fifth largest current out of nine currents is extracted. Anextension to the basic median filtering is described e.g., in L. Yin,R.Yang, M. Gabbouj and Y. Neuvo, “Weighted Median Filters: A Tutorial”,IEEE Transaction on Circuits and Systems—II, Vol. 43, pages 157-192,1996, where each input can be given different weights to favor theselection of certain variables. In this weighting scheme a weight of amagnitude e.g., three assigned to a certain variable means practicallythat the variable is entered three times to the list of variables out ofwhich the median is selected. This also means that the total number ofvariables out of which the selection is to be made has increased by two.

[0007] There has been described some analog implementations forfiltering images. In an article by G.Fikos, S.Vlassis, and S.Siskos,“High-Speed, Accurate Analogue CMOS Rank Filter”, Electronics Letters,Vol. 36, No. 7, pages 593-594, 2000, there is proposed a current-moderank extractor in which a circuit is suitable for multiple inputs.Furthermore, the extracted rank is selectable, i.e., the rank filteringinvolves the selection of the kth largest current I(k). A basic cell ofthe implementation is a current comparator, which has an output current.The basic cell contains two different building blocks, one to performthe actual comparison and one to provide the current output. The currentoutput of the basic cell is realized by complementary current sources,i.e., one source provides positive output currents and the otherprovides negative output currents, with switches at their outputs. Themagnitudes of the output currents of these current sources are assumedto have equal magnitudes inside one basic cell, and also within thewhole system. Thus the system is not able to perform weighted rankedorder filtering. The output switches are controlled by a voltage that isgenerated inside the basic cell by a current comparator with voltageoutput. A plurality of basic cells provide their current output to acommon node where the sum of the output currents is compared to anothercurrent. This another current is generated by a current source that mustbe able to provide both positive or negative currents, one polarity atthe time, and by controlling the magnitude and sign of this particularcurrent source input currents to the system that have a predeterminedranked order can be extracted.

[0008] The analog implementations for processing images described inprior art do not allow programmable function or they are too complex tobe integrated into a chip in large numbers of processors. Some of thestructures described in prior art also have essentially high powerconsumption, and therefore, it is not preferred to integrate thousandsof processors into a chip.

SUMMARY OF THE PRESENT INVENTION

[0009] It is an object of the present invention to overcome or at leastmitigate the disadvantages of the prior art. The present inventionprovides a processor, a circuit and a method that enable smallerprocessors in an analog parallel processor network.

[0010] According to a first aspect of the present invention there isprovided a processor in an analog parallel processor network, for imageprocessing, the processor comprising:

[0011] a plurality of circuits, wherein a circuit comprises a firsttransistor and a second transistor, which receive respective supplyvoltages and operate as current sources, providing an output voltage,and a coefficient coupling, which receives the output voltage providedby the first transistor and the second transistor, providing a switchingfunction for a circuit output current;

[0012] a bias transistor; and

[0013] an output transistor.

[0014] Preferably, the bias transistor provides an output current thatis set to a value in which a current with a specific ranked order numberfrom the set of output currents of the first transistor, or respectivetransistors, can be determined.

[0015] Preferably, the output transistor provides an output current fromthe processor.

[0016] Preferably, the coefficient coupling comprises: a thirdtransistor, which operates as a current source and a fourth transistor,which provides a switching function. More preferably, the coefficientcoupling provides three modes of operation: the fourth transistorconducts the current, the fourth transistor conducts a limited amount ofthe current, or the fourth transistor does not conduct the current.

[0017] Preferably, the third transistor receives a coefficient voltagethat is programmable.

[0018] Preferably, the output voltage provided by the first transistorand the second transistor is the control voltage of the fourthtransistor.

[0019] Preferably, the first transistor has an inlet for the supplyvoltage and an inlet for a control voltage.

[0020] Preferably, the second transistor has an inlet for the supplyvoltage and an inlet for a control voltage, wherein the control voltageis formed from an output current of the fourth transistor together withother output currents received from respective transistors of aprocessor and from the bias transistor.

[0021] Preferably, at least one of the transistors is a PMOS transistor.

[0022] Preferably, at least one of the transistors is a NMOS transistor.

[0023] Preferably, the processor further comprising at least onetransistor for providing an output current that is summed up with thefirst transistor.

[0024] According to a second aspect of the present invention there isprovided a circuit for processing images in an analog parallel processornetwork, the circuit comprising:

[0025] a first transistor and a second transistor, which receiverespective supply voltages and operate as current sources, providing anoutput voltage; and

[0026] a coefficient coupling, which receives the output voltageprovided by the first transistor and the second transistor, providing aswitching function for a circuit output current.

[0027] According to a third aspect of the present invention there isprovided a method for processing images in an analog parallel processornetwork, the method comprising:

[0028] receiving a source voltage and a control voltage in a firsttransistor, and forming an output current of the first transistor;

[0029] receiving a source voltage and a control voltage in a secondtransistor, and forming an output current of the second transistor;

[0030] receiving a source voltage and a coefficient voltage in a thirdtransistor, and providing an input current to a fourth transistor;

[0031] receiving an input voltage, which is defined with respect to theoutput currents of the first transistor and the second transistor, andan input current from the third transistor in the fourth transistor;

[0032] determining a mode of operation in the fourth transistor based onthe input voltage and the input current; and

[0033] providing an output current of the fourth transistor for furtherprocessing.

[0034] Preferably, the coefficient voltage is programmable.

[0035] Preferably, the mode of operation is one of the following:

[0036] the fourth transistor conducts the input current;

[0037] the fourth transistor conducts a limited amount of the inputcurrent; or

[0038] the fourth transistor does not conduct the input current.

[0039] Preferably, the output current of the fourth transistor isprovided to form a control voltage of the second transistor, and otherrespective transistors in a processor, together with other outputcurrents received from respective transistors and from a bias transistorof the processor in an analog parallel processor network.

[0040] Preferably, the method further comprising a bias transistorproviding an output current that is set to a value in which a currentwith a specific ranked order number from the set of output currents ofthe first transistor, or respective transistors, can be determined.

[0041] According to a fourth aspect of the present invention there isprovided a processor for processing images in an analog parallelprocessor network, the processor comprising:

[0042] a plurality of circuits, wherein a circuit comprises a firsttransistor and a second transistor, which receive respective supplyvoltages and operate as current sources, providing an output voltage anda third transistor, which receives a source voltage and the outputvoltage provided by the first transistor and the second transistor,providing a switching function for a circuit output current;

[0043] a bias transistor, which provides an output current that is setto a value in which a current with a specific ranked order number fromthe set of the first transistor, or respective transistors, can bedetermined; and

[0044] an output transistor for providing an output current of theprocessor to following process.

[0045] According to a fifth aspect of the present invention there isprovided a method for processing images in an analog parallel processornetwork, the method comprising:

[0046] receiving a source voltage and a control voltage in a firsttransistor, and forming an output current of the first transistor;

[0047] receiving a source voltage and a control voltage in a secondtransistor, and forming an output current of the second transistor;

[0048] receiving an input voltage, which is defined with respect to theoutput currents of the first transistor and the second transistor, and asource voltage in a third transistor;

[0049] determining a mode of operation in the third transistor based onthe source voltage and the input voltage;

[0050] providing an output current of the third transistor for furtherprocessing;

[0051] forming a control voltage of the second transistor from theoutput currents of at least one third transistor and a bias transistorof a processor, wherein the output current of the bias transistor is setto a value in which a current with a specific ranked order number from aset of output currents of the first transistors can be determined; and

[0052] conducting the control voltage to at least one second transistorin the processor.

[0053] The present invention provides a simple analogue implementation,which can be programmed according to a ranked order number or to aweighted coefficient. The present invention further achieves lower powerconsumption than the prior art implementations. The present invention isalso easy to implement to an existing system, because the presentinvention implements the transistors that already exist in processorunits for processing images.

BRIEF DESCRIPTION OF THE DRAWINGS

[0054] For a better understanding of the present invention and in orderto show how the same may be carried into effect reference will now bemade, by way of example, to the accompanying drawings, in which:

[0055]FIG. 1 shows a coefficient coupling that is implemented in thepreferred embodiment of the present invention.

[0056]FIG. 2 shows a structure, having two current sources, and a resultoutput voltage, according to a preferred embodiment of the presentinvention.

[0057]FIG. 3 shows an inventive concept of the present invention.

[0058]FIG. 4 shows an alternative embodiment of the inventive concept ofthe present invention.

[0059]FIG. 5 is a flowchart illustrating the method of the preferredembodiment of the present invention.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

[0060] The present invention is designed for implementation in an analogparallel processor network, although it may also be implemented suchthat only one circuit is implemented to a system. The present inventionmay be implemented to process and/or analyze images, and achieves ahigh-speed calculation (over 10¹² calculations per second) in one chip.

[0061]FIG. 1 shows a coefficient coupling that is implemented in thepreferred embodiment of the present invention. In this exemplaryillustration, the coefficient coupling has two transistors 101, 102. Thefirst transistor 101 has an inlet 103 for a source voltage, and an inlet104 for a coefficient voltage. Furthermore, the first transistor 101 hasan outlet 105 for providing a current to the second transistor 102,i.e., the first transistor 101 is a current source of the secondtransistor 102. The coefficient voltage used in the present invention isprogrammable. The coefficient voltage may be programmed e.g., accordingto weight values predetermined by weighted ranked order filteringalgorithms.

[0062] The second transistor 102 has an inlet 106 for the currentconducted from the first transistor 101 and an inlet 107 for a controlvoltage. The second transistor 102 also has an outlet 108 for an outputcurrent. The second transistor 102 operates as a switch in a coefficientcoupling, determining modes of operation.

[0063] In the present invention, there are three modes of operation fora coefficient coupling circuit. The first mode of operation is when theswitch conducts the whole current without restricting the amount of thecurrent provided by a current source. In a first mode of operation thecontrol voltage of the second transistor is high enough that therestriction of the current does not occur. Usually this voltage is inclose proximity to the positive supply voltage. In such case, thecoefficient voltage of the first transistor defines the output current.In a second mode of operation, a switch conducts some amount of currentbut restricts the amount of the current provided by the current source.When the second mode of operation occurs, the output current of thecoupling is between the current value provided by the current source inan unlimited case and 0. In a third mode of operation, the switch doesnot conduct the current at all. In the third mode of operation, theswitch does not conduct the current, because the control voltage is inlow level, and therefore, the output current of the coefficient couplingis 0. In this exemplifying presentation, the current source is aPMOS-transistor and the switch is a NMOS-transistor. Another possibilityis to form a coefficient coupling, wherein a current source is aNMOS-transistor and a switch is a PMOS-transistor. In this case, thepolarities of the voltages are opposite, i.e., a high voltage in theabove description will be a low voltage in this case and contrary.

[0064]FIG. 2 shows a structure having two current sources, i.e.,transistors 201 and 202. The first transistor 201 has an inlet 203 for asource voltage, and an inlet 204 for a control voltage. Furthermore, thefirst transistor 201 has an outlet 205 for providing a current to thesecond transistor 202. The second transistor 202 has an inlet 206 for asource voltage, and an inlet 207 for a control voltage. The secondtransistor 202 further has an outlet 208 for an output current. FIG. 2also shows an output voltage that is a result voltage occurred from therelative current value difference between the current received from thefirst transistor 201 and the current received from the second transistor202.

[0065] In the structure according to FIG. 2, the first transistor 201tends to feed an output current through the second transistor 202. Thevalue of the current provided by the first transistor 201 is dependenton the control voltage of the first transistor 201. The secondtransistor 202 is able to let through a current, which is defined by thecontrol voltage of the second transistor 202.

[0066] Depending on the relative values of the unrestricted outputcurrents of the first transistor 201 and the second transistor 202, theresult output voltage is in close approximate whether to a sourcevoltage received in the first transistor 201 or to a source voltagereceived in the second transistor 202, the result value may also be inbetween these values. In case the unrestricted output current of thefirst transistor tends to be larger than the unrestricted output currentof the second transistor, the result output value is in closeapproximate to the source voltage of the first transistor. In case theunrestricted output current of the second transistor tends to be largerthan the unrestricted output current of the first transistor, the resultoutput voltage value is in close approximate to the source voltage ofthe second transistor. In case the unrestricted output currents areessentially equal, the result output voltage is between the values ofthe source voltages of the first transistor and the second transistor.

[0067]FIG. 3 shows an inventive concept of the present invention. FIG. 3shows three circuits 301, 302 and 303, each of which comprises fourtransistors, a bias transistor 370 and an output transistor 380. Circuit301 comprises four transistors 310, 311, 312 and 313, from which thetransistors 310 and 311 forms a structure disclosed with reference to aFIG. 2, and transistors 312 and 313 forms a coefficient couplingdisclosed with reference to FIG. 1. The transistor 310 functions as thefirst transistor 201 in FIG. 2, having similar inlets and an outlet,i.e., an inlet 314 for a source voltage, an inlet 315 for a controlvoltage, and an outlet 316 for providing a current to a followingtransistor 311. The transistor 311 functions as the second transistor202 in FIG. 2, having similar inlets and an outlet, i.e., an inlet 317for a source voltage, an inlet 318 for a control voltage, and an outlet319 for providing an output current. Transistors 312 and 313 form acoefficient coupling, which corresponds to the coefficient couplingdisclosed with reference to FIG. 1, having similar inlets (320, 321, 323and 324) and outlets (322 and 325). The coefficient coupling (i.e.,transistors 312 and 313) functions the same way as the coefficientcoupling in FIG. 1. Circuit 302 (circuit 303) comprises the transistors330-333 (350-353), having inlets and outlets 334-345 (354-365), whichcorrespond to the transistors 310-313 and the inlets and outlets 314-319of the circuit 301. A bias transistor 370 has an inlet 371 for a sourcevoltage, an inlet 372 for a control voltage and an outlet 373 forproviding an output current of the bias transistor 370. An outputtransistor 380, in turn, has an inlet 381 for a source voltage, an inlet382 for a control voltage and an outlet 383 for providing an outputcurrent of the system. The output current of the output transistor 380may be conducted e.g., to another processor in a parallel processornetwork or to a memory unit.

[0068] The apparatus of FIG. 3 is capable to evaluate the first, secondand third biggest of the output currents of the transistors 310, 330 and350. A skilled person in the art appreciates that even though there isonly three circuits presented in this presentation, the number ofcircuits, and therefore also the number of the output currents of thefirst transistors, may be different (e.g., four or more), and the sameevaluation procedure still applies to the system.

[0069] It may be a situation that there is a need to add somenon-negative current into every input current of the system, whenimplementing mathematical morphology. In this situation, there is one ormore transistors similar to the first transistor in every circuit,wherein an output current of the added transistor(s) is (are) summed upwith the output current of the first transistor to form a sum outputcurrent of these transistors, which will be evaluated in a same way asthe output current of the first transistor in the following simplifiedpresentation of the process applied in the present invention. The addedtransistor(s) is (are) similar to the first transistor, i.e., in casethe first transistor is a PMOS transistor the added transistor(s) is(are) also a PMOS transistor(s). If the first transistor type is a NMOStransistor, the added transistor(s) is (are) also a NMOS transistor(s)

[0070] In this exemplifying presentation, the transistors 380, 311, 331and 351 are of the same size, and because they have the same controlvoltage (Vcont) and the same supply voltages, it can be understood thatunrestricted output currents of the transistors 380, 311, 331 and 351are of the same value.

[0071] As for exemplifying purposes, the output current of thetransistor 310 is greater than the output current of the transistor 330,which in turn is greater than the output current of the transistor 350.The transistors 311, 331 and 351, which are for example NMOStransistors, provide equal output currents in an unrestricted case.Further, the control voltages of the transistors 312, 332 and 352 are ofthe same value, and the sizes of the transistors 312, 332 and 352 arethe same. Even though, the control voltages and the sizes of thetransistors 312, 332 and 352 are of the same in this exemplifyingpresentation, they are of the same size for simplifying thepresentation. The control voltages and the sizes of the transistors 312,332 and 352 can differ for example so that the output currents of thetransistors 312, 332 and 352 are defined in relation to a weightedcoefficient, e.g., the output current of the transistor 332 is threetimes as big as the values of the output currents of the transistors 312and 352. The unrestricted output current of the transistors 312, 332 and352 is called a reference current (Iref). In a stable equilibrium someof the output currents of transistors 312, 332 and 352 may not berestricted by the accompanying switch transistors 313, 333 and 353,respectively, some of the output currents may be restricted by theswitches and some output currents may be 0 corresponding to the threemodes of operation described with reference to FIG. 1. The equilibriumconditions are controlled by a bias current, the output current of thebias transistor 370, in such a way that the sum of the output currentsthrough switches 313, 333 and 353 equals the output current of the biastransistor 370.

[0072] First, the biggest value of the output currents of thetransistors 310, 330, and 350 will be examined. The output current valueof the bias transistor 370 is chosen to be between the reference currentvalue and 0 (with a restriction that the value should not be exactly 0).The value of the output current of the bias transistor 370 can be, forexample, half of the value of the reference current. Then theequilibrium of the system is as follows. The voltage (Vcont), which isalso a control voltage of the transistors 311, 331, and 351, will besuch a value that the output current value of the transistor 311 will beequal to the output current value of the transistor 310. In thissituation, the transistor 313 will conduct part of the output current ofthe transistor 312, and the value of the output current of thetransistor 313 equals to the output current value of the bias transistor370. Because the value of the output current of the transistor 331 isgreater than the value of the output current of the transistor 330, thepotential value of the control voltage of the transistor 333 will get solow that the transistor 333 does not conduct the output current of thetransistor 332, i.e., the value of the output current of the transistor333 equals to 0. In this situation, the same may be applied to thecircuit 303, i.e., the value of the output current of the transistor 353will equal to 0. Because the control voltage of the output transistor380 is also Vcont, the value of the output current of the outputtransistor 380 will equal to the values of the output currents of thetransistors 310 and 311 (which are equal), i.e., the output current ofthe output transistor 380 equals to the biggest value of the outputcurrents of the transistors.

[0073] Now we will present how the second biggest output current valueof the transistors 310, 330, and 350 will be evaluated. For achievingthis result, the input current value of the bias transistor 370 will bechosen to be between the values of the reference current (Iref) and thereference current multiplied by two (2*Iref), e.g., the value of theinput current of the bias transistor 370 is reference current multipliedby 1,5 (1,5*Iref). In such a situation, the equilibrium of the system isfollowing. The control voltage of the transistors 313, 333, and 353 willbe such a value, in which the values of the output currents of thetransistors 330 and 331 will be equal. In this situation, the value ofthe output current of the transistor 310 is bigger than the value of theoutput current of the transistor 311, and therefore, control voltage ofthe transistor 313 will grow until the transistor 313 conducts theoutput current of the transistor 312. The output current value of thetransistor 333 equals to the value where the output current value of thebias transistor 370 is deducted by the output current value of thetransistor 310, which in this case equals to the reference current(Iref). Because the value of the output current of the transistor 351 isgreater than the value of the output current of the transistor 350, thepotential value of the control voltage of the transistor 353 will get solow that the transistor 353 does not conduct the output current of thetransistor 352, i.e., the value of the output current of the transistor353 equals to 0. In the equilibrium of the system, the output currentvalue of the transistor 331 equals to the output current value of thetransistor 330, and because the control voltages of the transistor 331and the output transistor 380 are equal, also the output current of thesystem equals the output current of the transistor 330.

[0074] If the third biggest value of the output currents of thetransistors 310, 330 and 350 will be evaluated, the following processcan be applied. It is known that the third biggest output current valueis also the smallest output current value, which in this example is theoutput current value of the transistor 350. In this example, we will setthe bias current between 2*Iref and 3*Iref, for example bias currentequals to 2,5*Iref. In such a situation, the equilibrium of the systemis when the switches 313 and 333 conduct the respective currents andswitch 353 conducts a limited amount of the current received from thetransistor 352. In this case the output current of the output transistor380 equals to output current of the transistor 351, which also equals tothe output current of the transistor 350.

[0075] Even though in the above embodiment, the biggest output currentvalue were analyzed, where after the second biggest output current valuewere analyzed, it is not necessary to analyze the output current valuesin this specific order. The present invention enables to find any outputcurrent value. In general, it is possible to find any ordered outputcurrent value, when the bias current value is set between (N−1*Iref andN*Iref, wherein N equals to the ranked order number that is wanted to befound and Iref is the reference value described in the previousparagraphs. In the present invention, it is possible to use thefollowing formula for a bias current to select the ranked order (e.g.,the sixth biggest) input current:

(((N−1+N)/2)*Iref

[0076] When analyzing with the above formula, which transistor has thesixth biggest output current value, N equals to 6 and the bias currentvalue therefore equals to 5,5*Iref.

[0077] When implementing an analog parallel processor network accordingto the present invention, the analog parallel processor networkcomprises a plurality of processors. The analog parallel processornetwork further comprises a plurality of memory units. The outputcurrent of the output transistor 380 is provided to a memory unit in ananalog parallel processor network, where from the memory unit canprovide a voltage to the inlets 315 (335 and 355 respectively) of thetransistors 310 (330 and 350 respectively) of another processor.

[0078] In an alternative embodiment of the present invention, thecoefficient coupling, shown in FIG. 3, is replaced with a different kindof coupling. In this embodiment of the present invention the couplingcomprises only one transistor. The object of the alternative embodimentof the present invention is to minimize the space required for oneprocessor in the chip. As for achieving this result, the programmablefunction of the coefficient coupling has to be compromised.

[0079] In this alternative embodiment of the present invention, thetransistors 312, 332 and 352 are deleted from the circuits 301, 302 and303. Each one of the transistors 313, 333 and 353 receives a sourcevoltage and provides an output current to further processing accordingto the switching function of the transistors 313, 333 and 353. Thesource voltage is preferably set low enough in order to keep the unitycurrent (i.e., Iref) practically low.

[0080] Except for the simplified structure of the coupling (andelimination of the coefficient structure of the coupling) that providesswitching function of the circuit, the process of the structure remainsessentially similar to the preferred embodiment of the present inventionthat is described with respect to FIG. 3.

[0081]FIG. 4 shows an alternative embodiment of the inventive concept ofthe present invention. FIG. 4 shows three circuits 401, 402 and 403,each of which comprises four transistors, a bias transistor 470 and anoutput transistor 480. Circuit 401 comprises four transistors 410, 411,412 and 413. The transistor 410 has an inlet 414 for a source voltage,an inlet 415 for a control voltage, and an outlet 416 for providing anoutput current of the transistor 410. The transistor 411 has an inlet417 for a source voltage, an inlet 418 for a control voltage, and anoutlet 419 for providing an output current. Transistors 412 and 413 forma coefficient coupling having inlets 420, 421, 423 and 424 and outlets422 and 425. The coefficient coupling (i.e., transistors 412 and 413)functions the same way as the coefficient coupling in FIG. 3 except thetransistors 412 and 413 are of the same type, e.g., PMOS transistors.This change of the type of the switching transistor 413 also changes thelogic when the switch 413 does or does not conduct to the opposite. Thischange of modes of operation also requires the use of the current mirror490 to negate the combined current received from the transistors 413,433 and 453. The current mirror 490 has two transistors 491 and 492,which in turn have inlets 493 and 495 and outlets 493 and 496.Furthermore, the bias transistor 470 has also been changed to a PMOStransistor. Also the transistor 410 has been changed from a PMOStransistor into a NMOS transistor, and the transistor 411 has beenchanged from a NMOS transistor into a PMOS transistor.

[0082] Circuit 402 (circuit 403) comprises the transistors 430-433(450-453), having inlets and outlets 434-445 (454-465), which correspondto transistors 410-413 and the inlets and outlets 414-419 of the circuit401. A bias transistor 470 has an inlet 471 for an input current, aninlet 472 for a control voltage and an outlet 473 for providing anoutput current of the bias transistor 470. An output transistor 480, inturn, has an inlet 481 for an input current, an inlet 482 for a controlvoltage and an outlet 483 for providing an output current of the system.The output current of the output transistor 480 may be conducted e.g.,to another processor in a parallel processor network or to a memoryunit.

[0083] As in the preferred embodiment of the present invention (asdescribed with reference to FIG. 3), the alternative embodiment of thepresent invention is also capable to evaluate the current with aspecific ranked order number from the set of the output currents of thetransistors 410, 430 and 450. The same may be applied to the processorsthat have e.g., nine circuits, with similar evaluation procedure asapplied to the alternative embodiment of the present invention.

[0084] There also may be one or more transistors similar to the firsttransistor added in every circuit, wherein an output current of theadded transistor(s) is (are) summed up with the output current of thefirst transistor to form a sum output current of these transistors,which will be evaluated in a same way as the output current of the firsttransistor in the following simplified presentation of the processapplied in the present invention. The added transistor(s) is (are)similar to the first transistor, i.e., in case the first transistor is aPMOS transistor the added transistor(s) is (are) also a PMOStransistor(s). If the first transistor type is a NMOS transistor, theadded transistor(s) is (are) also a NMOS transistor(s)

[0085] In this exemplifying presentation, the transistors 480, 411, 431and 451 are of the same size, and because they have the same controlvoltage (Vcont) and the same supply voltages, it can be understood thatoutput currents of transistors 480, 411, 431 and 451 are of the samevalue.

[0086] As for exemplifying purposes, the output current of thetransistor 410 is greater than the output current of the transistor 430,which in turn is greater than the output current of the transistor 450.The transistors 411, 431 and 451 provide equal output currents in anunrestricted case. Further, the control voltages of the transistors 412,432 and 452 are assumed here to have the same value, and the sizes ofthe transistors 412, 432 and 452 are the same. The unrestricted outputcurrent of transistors 412, 432 and 452 is called a reference current(Iref).

[0087] In this exemplary presentation, we will define the biggest valueof the output currents of the transistors 410, 430 and 450. The outputcurrent value of the bias transistor 470 will be set to equal half ofthe reference current (0,5*Iref). In a stable equilibrium, the outputcurrent of the transistor 492 of the current mirror 490 equals to theoutput current of the bias transistor 470, i.e., the input current (sumcurrent of the output currents of the transistors 413, 433 and 453) ofthe current mirror equals to the output current of the bias transistor470. The control voltage (Vcont) has been set to a value, in which theoutput current of the transistor 411 equals to the output current of thetransistor 410, and therefore, the transistor 413 conducts partly theoutput current of the transistor 412.

[0088] Because the value of the output current of the transistor 431 isgreater than the value of the output current of the transistor 430, thepotential value of the control voltage of the transistor 433 will get sohigh that the transistor 433 does not conduct the output current of thetransistor 432, i.e., the value of the output current of the transistor433 equals to 0. In this situation, the same may be applied to circuit403, i.e., the value of the output current of the transistor 453 willequal to 0. Because the control voltage of the output transistor 480 isalso Vcont, the value of the output current of the output transistor 480will equal to the values of the output currents of the transistors 410and 411 (which are equal), i.e., the output current of the outputtransistor 480 equals to the biggest value of the output currents of thetransistors.

[0089] The other two output currents of the transistors 410, 430 and 450can be extracted by setting the output current value of the biastransistor 470 to equal 1,5*Iref (when evaluating the second biggestvalue of the transistors 410, 430 and 450), setting the output currentvalue of the bias transistor 470 to equal 2,5*Iref (when evaluating thethird biggest value of the transistors 410, 430 and 450.) The formula tofind out, which transistor has e.g., the sixth biggest output currentvalue presented with reference to FIG. 3 also applies to the alternativeembodiment of the present invention described with reference to FIG. 4.

[0090] In an alternative embodiment of the present invention, thecoefficient coupling, shown in FIG. 4, is replaced with a different kindof coupling. In this embodiment of the present invention the couplingcomprises only one transistor.

[0091] In this alternative embodiment of the present invention, thetransistors 412, 432 and 452 are deleted from the circuits 401, 402 and403. Each one of the transistors 413, 433 and 453 receives a sourcevoltage and provides an output current to further processing accordingto the switching function of the transistors 413, 433 and 453. Thesource voltage is preferably set low enough in order to keep the unitycurrent (i.e., Iref) practically low.

[0092] Except for the simplified structure of the coupling (andelimination of the coefficient structure of the coupling) that providesswitching function of the circuit, the process of the structure remainsessentially similar to the preferred embodiment of the present inventionthat is described with respect to FIG. 4.

[0093] When implementing an analog parallel processor network accordingto the present invention, the analog parallel processor networkcomprises a plurality of processors. The analog parallel processornetwork further comprises a plurality of memory units. The outputcurrent of the output transistor 480 is provided to a memory unit in ananalog parallel processor network, where from the memory unit provides avoltage to the inlet 417 (437 and 457 respectively) of the transistors410 (430 and 450 respectively) of another processor.

[0094] Referring now to FIG. 5, which is a flowchart illustrating themethod of the preferred embodiment of the present invention. In FIG. 5on step 501, a first transistor receives a source voltage and a controlvoltage of the system, and forms an output current of the firsttransistor. Essentially at the same time, a second transistor receives asource voltage and a control voltage of the system, and provides anoutput current of the second transistor (step 502). The first transistortends to feed an output current through the second transistor. Dependingon the relative values of the unrestricted output currents of the firsttransistor and the second transistor, the result output voltage is inclose approximate whether to the source voltage received in the firsttransistor or to the source voltage received in the second transistor.Essentially at the same time with the steps 501 and 502, a thirdtransistor receives a source voltage and a coefficient voltage andprovides an input current to a fourth transistor (step 503). Thecoefficient voltage received in the third transistor can beprogrammable. On step 504, the fourth transistor receives an inputvoltage (which is a control voltage of the fourth transistor) defined bythe output currents of the first transistor and the second transistor,and an input current received from the third transistor in the fourthtransistor.

[0095] On step 505, the fourth transistor determines a mode of operationbased on the input voltage received from the first transistor and thesecond transistor, and the input current received from the thirdtransistor. In case the output current value of the first transistor isgreater than the output current value of the second transistor, thefourth transistor conducts the whole input current received from thethird transistor without restricting the amount of the current providedby the third transistor (step 506). In this case the input currentreceived from the third transistor defines the output current of thefourth transistor. In case the output current of the second transistoris essentially equal to the output current of the first transistor, thefourth transistor conducts a limited amount of the input currentreceived from the third transistor in the fourth transistor (step 507).In this case, the output current of the fourth transistor is between theinput current value of the fourth transistor and 0. Preferably, thevalue of the output current of the fourth transistor equals to an outputcurrent value of a bias transistor of the system, if a maximum currentis extracted. Otherwise, the value of the output current of the fourthtransistor should essentially equal to a value that is the outputcurrent of the bias transistor minus (N−2)*Iref, wherein N equals to theranked order number that is extracted. If the output current valueprovided by the second transistor is greater than the output currentvalue provided by the first transistor, the potential value of thecontrol voltage of the fourth transistor will get such that the fourthtransistor does not conduct the input current received from the thirdtransistor in the fourth transistor (step 508), i.e., the output currentof the fourth transistor is essentially equal to 0.

[0096] On step 509, the output current of the fourth transistor isprovided for further processing in the system. On step 510, a controlvoltage of the second transistor, and other respective transistors in aprocessor, is formed from the output current of the fourth transistortogether with other output currents received from respective transistorsof the processor. The sum current of the output current of the fourthtransistor and other output currents received from respectivetransistors and a bias transistor of the processor forms a controlvoltage (Vcont), which is conducted to the second transistor andrespective transistors in the processor. The control voltage (Vcont) isalso conducted to a bias transistor. The bias transistor output currentis set to a value in which a current with a specific ranked order numberfrom the set of the output currents of the first transistors can bedetermined (step 511). The bias current, i.e., the output current of thebias transistor, controls an equilibrium conditions in such a way thatthe sum of the output currents of the fourth transistor and itsrespective transistors in the processor equals to the output current ofthe bias transistor. This can be implemented because the control voltageof the bias transistor can be programmed to a certain value.

[0097] When evaluating a ranked order of the output currents of thefirst transistor and the respective transistors in a processor, themethod described with reference to FIGS. 3 and 4 can be applied.

[0098] Even though the method of the present invention has beenpresented with steps in a specific order in this presentation, a skilledperson in the art appreciates that almost every step occurs essentiallyat the same time in a circuit. Furthermore, only the steps 501, 503 and511 remains constant during the processing, and the other steps, i.e.,steps 502, 504-510, takes place all the time until the equilibrium ofthe system has been achieved.

[0099] In an alternative method of the present invention, the step 503is eliminated, and the ‘fourth transistor’ (which is a third transistorin the alternative embodiment of the present invention) receives asource voltage directly (in the preferred embodiment of the presentinvention the third transistor received the source voltage and providedan input current of the fourth transistor to the fourth transistor). Thealternative embodiment of the present invention corresponds to thepreferred embodiment of the invention in other steps than the step 503.

[0100] It will be appreciated by the skilled person that variousmodifications may be made to the above-described embodiments withoutdeparting from the scope of the present invention, as disclosed in theappended claims. For example the number of circuits, in a processor inan analog parallel processor network, that will be evaluated is usuallygreater than 3. Even though the number of circuits, and therefore, alsothe number of the output currents of the first transistor and therespective transistors in a processor differ, the same evaluationprocedure as disclosed in this presentation still applies to the system.

1. A processor in an analog parallel processor network, for imageprocessing, the processor comprising: a plurality of circuits, wherein acircuit comprises a first transistor and a second transistor, whichreceive respective supply voltages and operate as current sources,providing an output voltage, and a coefficient coupling, which receivesthe output voltage provided by the first transistor and the secondtransistor, providing a switching function for a circuit output current;a bias transistor; and an output transistor.
 2. A processor according toclaim 1, wherein the bias transistor provides an output current that isset to a value in which a current with a specific ranked order numberfrom the set of output currents of the first transistor, or respectivetransistors, can be determined.
 3. A processor according to claim 1 or2, wherein the output transistor provides an output current from theprocessor.
 4. A processor according to any one of the preceding claims,wherein the coefficient coupling comprises: a third transistor, whichoperates as a current source; and a fourth transistor, which provides aswitching function.
 5. A processor according to any one of the precedingclaims, wherein the coefficient coupling provides three modes ofoperation: the fourth transistor conducts the current; the fourthtransistor conducts a limited amount of the current; or the fourthtransistor does not conduct the current.
 6. A processor according to anyone of the preceding claims, wherein the third transistor receives acoefficient voltage that is programmable.
 7. A processor according toany one of the preceding claims, wherein the output voltage provided bythe first transistor and the second transistor is the control voltage ofthe fourth transistor.
 8. A processor according to any one of thepreceding claims, wherein the first transistor has an inlet for thesupply voltage and an inlet for a control voltage.
 9. A processoraccording to any one of the preceding claims, wherein the secondtransistor has an inlet for the supply voltage and an inlet for acontrol voltage, wherein the control voltage is formed from an outputcurrent of the fourth transistor together with other output currentsreceived from respective transistors of a processor and from the biastransistor.
 10. A processor according to any one of the precedingclaims, wherein at least one of the transistors is a PMOS transistor.11. A processor according to any one of the preceding claims, wherein atleast one of the transistors is a NMOS transistor.
 12. A processoraccording to any one of the preceding claims, wherein the processorfurther comprises at least one transistor for providing an outputcurrent that is summed up with the first transistor.
 13. A circuit forprocessing images in an analog parallel processor network, the circuitcomprising: a first transistor and a second transistor, which receiverespective supply voltages and operate as current sources, providing anoutput voltage; and a coefficient coupling, which receives the outputvoltage provided by the first transistor and the second transistor,providing a switching function for a circuit output current.
 14. Amethod for processing images in an analog parallel processor network,the method comprising: receiving a source voltage and a control voltagein a first transistor, and forming an output current of the firsttransistor; receiving a source voltage and a control voltage in a secondtransistor, and forming an output current of the second transistor;receiving a source voltage and a coefficient voltage in a thirdtransistor, and providing an input current to a fourth transistor;receiving an input voltage, which is defined with respect to the outputcurrents of the first transistor and the second transistor, and an inputcurrent from the third transistor in the fourth transistor; determininga mode of operation in the fourth transistor based on the input voltageand the input current; and providing an output current of the fourthtransistor for further processing.
 15. A method according to claim 14,wherein the coefficient voltage is programmable.
 16. A method accordingto claim 14 or 15, wherein the mode of operation is one of thefollowing: the fourth transistor conducts the input current; the fourthtransistor conducts a limited amount of the input current; or the fourthtransistor does not conduct the input current.
 17. A method according toany one of claims 14-16, wherein the output current of the fourthtransistor is provided to form a control voltage of the secondtransistor, and other respective transistors in a processor, togetherwith other output currents received from respective transistors and froma bias transistor of the processor in an analog parallel processornetwork.
 18. A method according to any one of the claims 14-17, whereinthe method further comprises a bias transistor providing an outputcurrent that is set to a value in which a current with a specific rankedorder number from the set of output currents of the first transistor, orrespective transistors, can be determined.
 19. A processor forprocessing images in an analog parallel processor network, the processorcomprising: a plurality of circuits, wherein a circuit comprises a firsttransistor and a second transistor, which receive respective supplyvoltages and operate as current sources, providing an output voltage anda third transistor, which receives a source voltage and the outputvoltage provided by the first transistor and the second transistor,providing a switching function for a circuit output current; a biastransistor, which provides an output current that is set to a value inwhich a current with a specific ranked order number from the set of thefirst transistor, or respective transistors, can be determined; and anoutput transistor for providing an output current of the processor tofollowing process.
 20. A method for processing images in an analogparallel processor network, the method comprising: receiving a sourcevoltage and a control voltage in a first transistor, and forming anoutput current of the first transistor; receiving a source voltage and acontrol voltage in a second transistor, and forming an output current ofthe second transistor; receiving an input voltage, which is defined withrespect to the output currents of the first transistor and the secondtransistor, and a source voltage in a third transistor; determining amode of operation in the third transistor based on the source voltageand the input voltage; providing an output current of the thirdtransistor for further processing; forming a control voltage of thesecond transistor from the output currents of at least one thirdtransistor and a bias transistor of a processor, wherein the outputcurrent of the bias transistor is set to a value in which a current witha specific ranked order number from a set of output currents of thefirst transistors can be determined; and conducting the control voltageto at least one second transistor in the processor.